1. Field of the Invention
The present invention generally relates to electronic devices, and more particularly, the present invention relates to a memory system and data processing techniques associated with memory systems.
2. Description of the Related Art
A flash memory device is a type of EEPROM wherein a plurality of memory regions are erased or programmed via one program operation. A conventional EEPROM enables one memory region to be erased or programmed at a stroke. This means that a flash memory device operates faster and at a more effective speed when systems using flash memory devices read and write to different memory regions at the same time. All types of flash memories and EEPROMs may wear out after a specific number of erase operations due to failure of the insulation film that surrounds the charge storing means used to store data.
An advantage of a flash memory device is that it may store information on a silicon chip in a manner whereby no power is needed to retain the stored information. This means that in the event power is cut off to the chip, information is retained without power consumption. Further characteristics of flash memory devices include impact resistance and rapid read access time. In view of these characteristics, flash memory devices are generally used for storage in devices which are supplied with power from a battery. Flash memory devices are divided into two types according to logic gate type, that is NOR flash memory devices and NAND flash memory devices.
A flash memory device stores information in an array of transistors each called a cell, which stores 1-bit information. Newer flash memory devices such as multi-level cell devices are capable of storing more than one bit per cell by varying an amount of charge applied to the floating gate of a cell.
In flash memory devices with floating gates, the most critical reliability concerns are data-retention characteristics and the number of program/erase cycles that may be performed without degradation (or endurance). The stored charge (electrons) can leak away from a floating gate by various failure mechanisms such as thermoionic emission and charge diffusion through defective interpoly dielectrics, ionic contamination, program disturb stresses, and the like. This causes a decrease in threshold voltage. The opposite effect of charge gain can occur when the floating gate slowly gains electrons with the control gate held at a voltage (e.g., a power supply voltage or a read voltage) due to a read disturbance, thus causing an increase in the threshold voltage.
As a result, the threshold voltage distribution of memory cells may be increasingly widened due to charge loss and charge gain. For example, assume that 2-bit data is stored in each memory cell. With this assumption, as illustrated in FIG. 1A, each memory cell may have one of an erase state E and three program states P1, P2 and P3. Ideally, constant cell margins (or read margins) exist between states E, P1, P2, and P3, whereby threshold voltage distributions 10, 11, 12, and 13 as shown respectively correspond to the states E, P1, P2, and P3. However, as illustrated in FIG. 1B, the threshold voltage distributions 10, 11, 12, and 13, particularly the threshold voltage distributions 11, 12, and 13 respectively corresponding to the program states P1, P2, and P3, are widened due to the above-described charge loss and charge gain. This means that the data read out from the memory cells may include many erroneous bits. In particular, this phenomenon becomes serious as the number of data bits stored in a memory cell is increased.